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X4C105
4K, NOVRAM/EEPROM
Data Sheet March 18, 2005 FN8124.0
CPU Supervisor with NOVRAM and Output Ports
FEATURES * 4Kbit serial EEPROM --400kHz serial interface speed --16-byte page write mode * One nibble NOVRAM --120ns NOVRAM access speed --AUTOSTORE --Direct/bus access of NOVRAM bits * Four output ports * Operates at 3.3V 10% * Low voltage reset when VCC < 3V --3% accurate thresholds available --Output signal shows low voltage condition --Activates NOVRAM AUTOSTORE --Internal block on EEPROM operation * Max EEPROM/NOVRAM nonvolatile write cycle: 5ms * High reliability --1,000,000 endurance cycles --Guaranteed data retention: 100 years * 20-lead TSSOP package
DESCRIPTION The low voltage X4C105 combines several functions into one device. The first is a 2-wire, 4Kbit serial EEPROM memory with write protection. A Write Protect (WP) pin provides hardware protection for the upper half of this memory against inadvertent writes. A one nibble NOVRAM is provided and occupies a single location. This allows access of 4-bits in a single 150ns cycle. This is useful for tracking system operation or process status. The NOVRAM memory is completely isolated from the serial memory section. A low voltage detect circuit activates a RESET pin when VCC drops below 3V. This signal also blocks new read or write operations and initiates a NOVRAM AUTOSTORE. The AUTOSTORE operation is powered by an external capacitor to ensure that the value in the NOVRAM is always maintained in the event of a power failure. The four NOVRAM bits also appear on four separate output pins to allow continuous control of external circuitry, such as ASICs. Intersil EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
BLOCK DIAGRAM
WP Write Control Logic HV Generation Timing and Control EEPROM Memory Static RAM Memory 4Kbits
Output Buffers and Latches
O0 O1 O2 O3 D0 D1 D2 D3 CE OE WE CAP VCC VSS RESET
Command Decode and Control Logic
X Decoder
SCL SDA S1 S2
EEPROM Array
I/O Buffers
Y Decoder Data Register Low Voltage Detect Power-on Reset
Control Logic and Timing Voltage Monitor Supply
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X4C105
PACKAGE/PINOUTS
20-Lead TSSOP CAP S1 S2 CE WE OE RESET O3 O2 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC WP SCL SDA D0 D1 D2 D3 O0 O1
A WP pin provides hardware write protection. The WP pin active (HIGH) prevents writes to the top half of the memory. This section is a 4K-bit version of an industry standard 24C04 device. NOVRAM Section The X4C105 also contains a single nibble of NOVRAM, with parallel access. This memory is completely isolated from the serial memory section. The NOVRAM is intended to connect to the system memory bus and uses standard CE, OE, and WE pins to control access. A NOVRAM (or nonvolatile RAM) consists of an SRAM part and an EEPROM part. The SRAM is saved to EEPROM only when power fails and the EEPROM is recalled to SRAM only on power-up. Output Ports
Pin Names Pin
VSS SDA VCC SCL WP S1, S2 CAP D0-D3 RESET CE OE WE O0-O3 Ground Serial Data Power Serial Clock Write Protect Device Select Inputs External AUTOSTORE Capacitor NOVRAM I/Os Low Voltage Detect Output NOVRAM Chip Enable NOVRAM Read Signal NOVRAM Write signal NOVRAM Outputs
Description
The X4C105 has four output only ports. These are active whenever power is applied to the device. The state of the output pin reflects the value in the respective SRAM bit. As such, these port pins provide a nonvolatile state. The conditions on the pins are restored when power is re-applied to the device. This can be valuable as a DIP switch replacement for controlling the conditions of an ASIC or other system logic. Low Voltage Detection When the internal low voltage detect circuitry senses that VCC is low, several things happen: - The RESET pin goes active. - The contents of the SRAM are automatically saved to the "shadow" EEPROM. - Internal circuitry switches to provide power for the AUTOSTORE operation from the CAP pin so the store operation can complete even in the event of a catastrophic power failure. To insure this, it is recommended that a 47F capacitor be used on the CAP pin. The capacitor is continuously charged during normal operation to provide the necessary charge to complete the store operation. Other internal circuits are turned off to minimize current consumption during the store operations. -- Communication to the device is interrupted and any command is aborted. If a serial nonvolatile store is in progress when power fails, the operation is completed and is followed by a NOVRAM AUTOSTORE cycle.
DEVICE DESCRIPTION Serial Memory Section The device contains a 4Kbit EEPROM memory array with an internal address counter that allows it to be read sequentially, through its entire address space after receiving only 1 full address. The serial interface includes a current address read that requires no input address, but allows reading of the entire array starting from the address plus one of the last read or write. The address counter is also used for the write operation where the user may enter up to a page of data (16 bytes) after supplying only 1 full address.
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Capacitor Backup Circuit The diagram in Figure 1 shows a representation of the capacitor backup circuit. Figure 1.
To Internal Voltage Supply
VCC VTRIP HIGH when VCC > VTRIP LOW when VCCStart NOVRAM AUTOSTORE
CAP
SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data Figure 2. Valid Data Changes on the SDA Bus
SCL
transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 2.
SDA Data Stable Data Change Data Stable
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Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 3. Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 2. Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. The device will respond with an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect or when the device is busy, such as during a nonvolatile write. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to standby mode and place the device into a known state.
Figure 3. Valid Start and Stop Conditions
SCL
SDA Start Stop
Figure 4. Acknowledge Response From Receiver
SCL from Master
1
8
9
Data Output from
Data Output from Receiver Start Acknowledge
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SERIAL WRITE OPERATIONS Byte Write For a write operation, the device requires the slave address byte and a word address byte. This gives the master access to any one of the words in the array. After receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 5. An attempted write to a protected block of memory will suppress the acknowledge bit and the operation will terminate. Figure 5. Byte Write Sequence
Signals from the Master S t a r t Slave Address Byte Address S t o p
Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to `0' on the same page. This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 5 bytes are written to locations 10 through 15, and the last 7 bytes are written to locations 0 through 6. Afterwards, the address counter would point to location 7 of the page that was just written. See Figure 6. If the master supplies more than 16 bytes of data, then new data over-writes the previous data, one byte at a time.
Data
SDA Bus Signals from the Slave
0 A C K A C K A C K
Figure 6. Writing 12 bytes to a 16-byte page starting at location 10.
7 Bytes
5 Bytes
Address =6
Address Pointer Ends Here Addr = 7
Address 10
Address n-1
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The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 7 for the address, acknowledge, and data transfer sequence. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be affected.
Figure 7. Page Write Operation
(1 < n < 16) Signals from the Master S t a r t Slave Address Byte Address Data (1) Data (n) S t o p
SDA Bus 0 Signals from the Slave A C K A C K A C K A C K
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Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master's byte load operation, the device initiates the internal non volatile write cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the slave address byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 8. Figure 8. Acknowledge Polling Sequence
Byte load completed by issuing STOP. Enter ACK Polling
Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address byte is set to one. There are three basic read operations: current address read, random read, and sequential read. Current Address Read Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the slave address byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to Figure 9 for the address, acknowledge, and data transfer sequence. It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Random Read
Issue START
Issue Slave Address Byte (Read or Write)
Issue STOP
NO ACK returned? YES NO Issue STOP
High Voltage Cycle complete. Continue command sequence?
YES Continue Normal Read or Write Command Sequence
PROCEED
A random read operation allows the master to access any memory location in the array. Prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address byte. After acknowledging receipts of the word address byte, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 10 for the address, acknowledge, and data transfer sequence.
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Figure 9. Current Address Read Sequence
Signals from the Master S t a r t Slave Address S t o p 1 A C K
SDA Bus Signals from the Slave
Data
Figure 10. Random Address Read Sequence
Signals from the Master S t a r t Slave Address Byte Address S t a r t Slave Address S t o p 1 A C K A C K A C K
SDA Bus Signals from the Slave
0
Data
The device offers a similar operation, called "Set Current Address," where the device ends the transmission and issues a stop instead of the second start, shown in Figure 10. The device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next current address read operation will then read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter "rolls over" to address 0000H and the device continues to output data for each acknowledge received. Refer to Figure 11 for the acknowledge and data transfer sequence. SERIAL DEVICE ADDRESSING Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several parts: - a device type identifier that is always `1010'. - two bits that provide the device select bits. - one bit that becomes the MSB of the address. - one bit of the slave command byte is a R/W bit. The R/W bit of the slave address byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 12.
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Figure 11. Sequential Read Sequence
Signals from the Master Slave Address S t o p
A C K 1 A C K
A C K
A C K
SDA Bus
Signals from the Slave
Data (1)
Data (2)
Data (n-1)
Data (n)
(n is any integer greater than 1)
After loading the entire slave address byte from the SDA bus, the device compares the device select bits with the status of the device select pins. Upon a correct compare, the device outputs an acknowledge on the SDA line. Slave Byte
1 0 1 0 S2 S1 A8 R/W
Write Protect Operations The WP pin provides write protection. The WP pin protects the upper half of the array. Table 1. Write Protected Areas WP Pin
LOW HIGH
Serial Memory Write Protection
Writes possible to all locations No writes to 100H-1FFH, writes possible to 000H to 0FFH
Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power-up condition.
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ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65C to +135C Storage temperature ......................... -65C to +150C Voltage on any pin with respect to ground .................................-1.0V to 7.0V DC output current ................................................ 5 mA Lead temperature (soldering, 10 seconds) ........ 300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC OPERATING CHARACTERISTICS VCC = 3.0 to 3.6V at -40C to +85C unless otherwise specified. Symbol
ICC1(1)
Parameter
Active supply current serial read or serial write (does not include the nonvolatile store operation) Average active supply current during serial nonvolatile store operation Active supply current volatile NOVRAM read
Min.
Max.
2.0
Unit
mA
Test Conditions
VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz, SDA = Read/Write Operation, CE, OE, WE, D0-D3 = VIH; O0-O3, RESET = Open CAP is tied to VCC; VCC > VTRIP VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 = VIL, CE, OE, WE, D0-D3 = VIH; O0-O3, RESET = Open CAP is tied to VCC. Test during the N.V. write cycle. VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 = VIL, WE = VIH; CE, OE = VIL, D0-D3, O0-O3, RESET = Open CAP is tied to VCC; VCC > VTRIP VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA = VIH; WP, S1, S2 =VIL, OE = VIH; CE, WE = VIL, D0-D3 = VIL or VIH, O0-O3, RESET = Open CAP is tied to VCC; VCC > VTRIP VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA, VIH; WP, S1, S2 = VIL, WE, CE, OE = VIH; D0-D3, O0-O3, RESET = Open CAP is tied to VCC, VCC < VTRIP for Store; VCC > VTRIP for Recall VIL = VCC x 0.1, VIH = VCC x 0.9, SCL, SDA, CE, WE, OE, D0-D3, = VIH, WP = VIL, O0-O3, RESET = Open; CAP is tied to VCC VIN = GND to VCC VSDA = GND to VCC; Device is in Standby(2)
ICC2(1)
3.0
mA
ICC3(1)
3.0
mA
ICC4(1)
Active supply current volatile NOVRAM write
3.0
mA
ICC5(1)
Average active supply current over NOVRAM store, or active current during recall Standby current
3.0
mA
ISB1(1)
50
A
ILI ILO VIL(3) VIH
(3
Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Schmitt trigger input hysteresis Output LOW voltage Output HIGH voltage VCC - 0.4 -0.5 VCC x 0.7 .05 x VCC
10 10 VCC x 0.3 VCC + 0.5
A A V V V
VHYS VOL VOH
0.4
V V
IOL = 2.0mA, VCC = 3.3V IOH = -1mA, VCC = 3.3V
Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. (3) VIL min. and VIH max. are for reference only and are not tested.
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CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 3.0-3.6V Symbol
CI/O(4) CIN(4)
Note:
Parameter
Input/output capacitance (SDA, D0-D3, O0-O3) Input capacitance (SCL, WP, CE, WE, OE, S1, S2)
Max.
8 6
Unit
pF pF
Test Conditions
VI/O = 0V VIN = 0V
(4) This parameter is periodically sampled and not 100% tested.
SERIAL NONVOLATILE WRITE CYCLE TIMING Symbol
tWC
Note:
(5)
Parameter
Write cycle time
Min.
Typ.(5)
3
Max.
5
Unit
ms
(5) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used.
SERIAL MEMORY AC CHARACTERISTICS Serial AC Test Conditions
Input pulse levels Input rise and fall times Input and output timing levels Output load VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Standard output load
Equivalent AC Output Load Circuit for VCC = 3.0-3.6V
3.3V
1533 SDA 100pF
For VOL = 0.4V and IOL = 2mA
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SERIAL AC SPECIFICATIONS TA = -40C to +85C, VCC = +3.0V to +3.6V, unless otherwise specified. 400kHz Option Symbol
fSCL tIN tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF tSU: S1, S2,WP tHD: S1, S2,WP Cb SCL clock frequency Pulse width of spikes to be suppressed by the input filter SCL LOW to SDA data out valid Time the bus must be free before a new transmission can start Clock LOW time Clock HIGH time Start condition setup time Start condition hold time Data in setup time Data in hold time Stop condition setup time Data output hold time SDA and SCL rise time SDA and SCL fall time S1, S2, and WP setup time S1, S2, and WP hold time Capacitive load for each bus line 20
Parameter
Min.
0 0 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 +.1Cb(8) 0.4 0.4
Max.
400 50 0.9
Unit
kHz ns s s s s s s ns s s ns
300 300
ns ns ms ms
20 +.1Cb(8)
400
pF
Notes: (7) This parameter is periodically sampled and not 100% tested. (8) Cb = total capacitance of one bus line in pF.
SERIAL TIMING DIAGRAMS Bus Timing
tF SCL tSU:STA SDA IN tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR
tAA SDA OUT
tDH
tBUF
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S1, S2, and WP Pin Timing
START SCL Clk 1 Slave Address Byte SDA IN tSU: S1,S2,WP S1, S2, and WP tHD: S1,S2,WP Clk 9
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK tWC Stop Condition Start Condition
NOVRAM AC CHARACTERISTICS NOVRAM AC Conditions of Test
Input pulse levels Input rise and fall times Input and output timing levels VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
1596
NOVRAM Equivalent A.C Load Circuits
3.3V
3093
30pF
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NOVRAM READ CYCLE SPECIFICATIONS Table 2. NOVRAM Read Cycle Limits VCC = 3.0V-3.6V -40C to +85C Symbol
tRC tCE tOE tOH tWES tWEH tLZ
(9)
Parameter
Read cycle time Chip enable access time Output enable access time Output hold from CE or OE HIGH Write enable HIGH setups time Write enable HIGH hold time Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output in high Z OE setup prior to operation in 2-wire mode OE hold following operation in 2-wire mode
Min.
Max.
120 50 50
Unit
ns ns ns ns ns ns ns ns
0 25 25 0 0 0 0 100 100 50 50
tOLZ(9) tHZ(9) tOHZ
(9)
ns ns ms ms
tSOE(9) tHOE(9)
Note:
(9) tLZ and tOLZ min.; tSOE and tHOE min; and tHZ and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.
NOVRAM Read Cycle
tRC tCE CE
tOE OE tWES WE tOLZ tLZ tHZ tOHZ tOH tWEH
D0-D3
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NOVRAM WRITE CYCLE SPECIFICATIONS NOVRAM Write Cycle Limits VCC = 3.0V-3.6V, TA = -40C to +85C Symbol
tWC tWC1 tOES tOEH tCW tCE tCH tWP tWP1 tWPH tDS tDH tNDO tSOE(10) tHOE(10) tWZ tOW tCHZ
(10) (10)
Parameter
Write cycle time Write cycle time Output enable HIGH setup time Output enable HIGH hold time Chip enable to end of write input Write setup time Write hold time Write pulse width Write pulse width Write pulse HIGH recovery time Data setup to end of write Data hold time New data output OE setup prior to operation in 2-wire mode OE hold following operation in 2-wire mode Write enable to output in HIGH-Z Output active from end of write Chip disable to output in high Z Output disable to output in high Z
Min.
120 170 50 50 50 0 0 50 100 50 40 0
Max.
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
50 100 100 50 0 0 0 50 50
ns ms ms ns ns ns ns
tOHZ
Note:
(10) tLZ and tOLZ min.; tSOE and tHOE min; and tHZ and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return high (whichever occurs first) to the time when the outputs are no longer driven.
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NOVRAM WE Controlled Write Cycle
OE
tOES tCW
tCH
CE tCE WE tWP tOEH tWPH tWC tDS D0-D3 (Data I/O) Data Valid tDH
tNDO O0-O3 (Data Out) Previous Valid Data New Valid Data
NOVRAM CE Controlled Write Cycle
OE tOES CE tCE tWP WE tWC tDS D0-D3 (Data In) Data Valid tDH tWPH tCH tCW tOEH
tNDO O0-O3 (Data Out) Previous Valid Data New Valid Data
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LOW VOLTAGE DETECT/POWER CYCLE PARAMETERS Symbols
VTRIP tRPD tPURST tF tR tOVT VRVALID Reset trip voltage-blank VCC detect to reset active Power-up reset time out delay (tPURST Option 1)-default VCC fall time from VCC = 3V to VCC = 2.5V VCC rise time from VCC = 2.5V to VCC = 3V Output pins valid after VCC exceeds VTRIP Reset valid VCC 1 100 100 100 200 200
Parameters
Min.
2.80
Typ.
2.875
Max.
2.95 500 400
Unit
V ns ms s s ns V
Low Voltage Detect and Output Pin Recall
VTRIP VCC tPURST tRPD tR RST tPURST tF VRVALID
tOVT Data Valid
tOVT VCC(min)
O0-O3
Data Valid
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PACKAGING INFORMATION 20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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Ordering Information X4C105 Device X X -X VCC Limits Blank = 3.3V 10%, VTRIP = 2.8-2.95V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Package V20 = 20 Lead TSSOP
Part Mark Convention 20-Lead TSSOP X4C105 YYWW XXX Blank = 3.3V 10%, 0 to +70C, VTRIP = 2.8-2.95V I = 3.3 10%, -40 to +85C, VTRIP = 2.8-2.95V
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FN8124.0 March 18, 2005

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